Recently, a variety of electronic appliances have become smaller in size and accommodate to a higher frequency, which results in requesting a chip type capacitor featuring a low impedance at a high frequency band, a small area occupied by its mounting on a circuit board. On the other hand, new CPUs (central processing unit) of computers consume less power and work faster, which requests the capacitor to have an excellent transient response as well as suppress heating resulting from current increase due to a higher speed. As a result, a capacitor having a large capacitance and a low equivalent series resistance (ESR) is demanded to meet the above requests.
One of the methods to enhance a capacitance of a chip type capacitor is disclosed in the Japanese Patent Application Unexamined Laid Open No. S57-157515, which teaches that a plurality of chip-type capacitors (elements) are piled up and integrated into one capacitor. To be more specific, two chip-type capacitor elements, i.e., the element formed by a rectangular tantalum solid electrolytic capacitor, of which opposite end faces extend terminal plates therefrom, are piled up and bonded each other. Then, the terminal plates of upper and lower elements are bent downward so that both plates are on top of the others, and the terminal plates thus situated are connected by soldering, thereby enhancing a capacitance of the chip-type tantalum solid capacitor.
However, since the terminal plates of this chip-type capacitor are coupled each other by soldering, when the chip-type capacitor is mounted to an electronic appliance by a reflow or flow soldering method, the solder between the terminal plates tends to be melted, whereby the terminal plates are vulnerable to disconnecting, which causes to lower the reliability from the connection view of point. Further, the tantalum solid electrolytic capacitor has not always a small ESR.